 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| HN28F101 Series 131072-word x 8-bit CMOS Flash Memory The Hitachi HN28F101 is a 131072-word x 8-bit CMOS flash Memory, realizing on-board programming. It programs or erases data with only on-board power supply (12 V VPP supply/5 V VCC supply). It programs data with fast programming algorithm by command inputs. It has two types of erase algorithm : automatic erase and fast erase by command inputs. Automatic erase function can erase data automatically without external control only by inputting trigger pulse and inform erase completion to CPU by status polling. The HN28F101 can control programming erase algorithm externally. * Erasing endurance: 10,000 times * Pin arrangement: 32-pin JEDEC standard * Package 32-pin DIP 32-pin SOP 32-pin TSOP 32-pin PLCC Ordering Information Type No. Access time Package --------------------------------------------- HN28F101P-12 120 ns 32-pin plastic ------------------------------ DIP HN28F101P-15 150 ns (DP-32) ------------------------------ HN28F101P-20 200 ns --------------------------------------------- HN28F101FP-12 120 ns 32-pin plastic ------------------------------ SOP HN28F101FP-15 150 ns (FP-32D) ------------------------------ HN28F101FP-20 200 ns --------------------------------------------- HN28F101T-12 120 ns 32-pin plastic ------------------------------ TSOP HN28F101T-15 150 ns (TFP-32DA) ------------------------------ HN28F101T-20 200 ns --------------------------------------------- HN28F101R-12 120 ns 32-pin plastic ------------------------------ TSOP HN28F101R-15 150 ns (TFP-32DAR) ------------------------------ HN28F101R-20 200 ns --------------------------------------------- HN28F101CP-12 120 ns 32-pin ------------------------------ PLCC HN28F101CP-15 150 ns (CP-32) ------------------------------ HN28F101CP-20 200 ns --------------------------------------------- Features * On-board power supply (VCC/VPP) VCC = 5 V 10% VPP = VSS to VCC (Read) VPP = 12.0 V 0.6 V (Erase/Program) * Fast access time 120 ns/150 ns/200 ns (max) * Programming function Byte programming Programming time: 25 s typ/byte Address, data, control latch function * On-board automatic erase function Chip erase Erase time: 1 s typ Address, data, control latch function Status polling function * Low power dissipation ICC = 10 mA typ (Read) ICC = 20 A max (Standby) IPP = 30 mA typ (Auto erase/Program) IPP = 20 A max (Read/Standby) HN28F101 Series Ordering Information (cont.) Type No. Access time Package --------------------------------------------- HN28F101TD-12 120 ns 32-pin plastic ------------------------------ TSOP HN28F101TD-15 150 ns (TFP-32D) ------------------------------ HN28F101TD-20 200 ns --------------------------------------------- HN28F101RD-12 120 ns 32-pin plastic ------------------------------ TSOP HN28F101RD-15 150 ns (TFP-32DR) ------------------------------ HN28F101RD-20 200 ns --------------------------------------------- HN28F101 Series Pin Description Pin name Function --------------------------------------------- A0-A16 Address --------------------------------------------- I/O0-I/O7 Input/output --------------------------------------------- CE Chip enable --------------------------------------------- OE Output enable --------------------------------------------- WE Write enable --------------------------------------------- VCC Power supply --------------------------------------------- VPP Programming power supply --------------------------------------------- VSS Ground --------------------------------------------- Pin Arrangement HN28F101P/FP Series HN28F101CP Series VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I /O0 I /O1 I /O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I / O7 I / O6 I / O5 I / O4 I / O3 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 4 3 2 1 32 31 30 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 14 15 16 17 18 19 20 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 A12 A15 A16 VPP VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O7 (Top view) 2 HN28F101 Series Pin Arrangement (cont) HN28F101T/TD Series HN28F101 Series A11 A9 A8 A13 A14 NC WE VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I / O7 I / O6 I / O5 I / O4 I / O3 VSS I / O2 I / O1 I / O0 A0 A1 A2 A3 (Top view) HN28F101R/RD Series OE A10 CE I / O7 I / O6 I / O5 I / O4 I / O3 VSS I / O2 I / O1 I / O0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 A14 NC WE VCC VPP A16 A15 A12 A7 A6 A5 A4 (Top view) 3 HN28F101 Series Block Diagram A5 A9 A12 A16 Address Latch X- Decoder HN28F101 Series 1024 X 1024 Memory Matrix I/O0 I/O7 Data Latch Input Data Control Y - Gating Y - Decoder Address Latch CE OE WE VCC VPP VSS Latch H H : High Threshold Inverter R/W/E Control A0 - A4, A10, A11 4 HN28F101 Series Mode Selection HN28F101 Series Pin ---------------------------------------------------------------- VPP CE OE WE A9 I/O0 - I/O7 DIP, SOP, PLCC (1) (22) (24) (31) (26) (13 - 15, 17 - 21) Mode TSOP (9) (30) (32) (7) (2) (21 - 23, 25 - 29) ----------------------------------------------------------------------------------------------- Read Read VCC*6 VIL VIL VIH A9 Dout ---------------------------------------------------------------------------------- Output disable VCC VIL VIH VIH X High-Z ---------------------------------------------------------------------------------- Standby VCC VIH X X X High-Z ---------------------------------------------------------------------------------- Identifier*1 VCC VIL VIL VIH VH*2 ID ----------------------------------------------------------------------------------------------- Command Read*3,*5 VPP VIL VIL VIH A9 Dout program ---------------------------------------------------------------------------------- Output disable VPP VIL VIH VIH X High-Z ---------------------------------------------------------------------------------- Standby VPP VIH X X X High-Z ---------------------------------------------------------------------------------- Write*4 VPP VIL VIH VIL A9 Din ----------------------------------------------------------------------------------------------- Notes: 1. Device identifier code can be output in command programming mode. Refer to the table of command address and data input. 2. VH: 11.5 < VH < 12.5V. 3. Data can be read when 12 V is applied to VPP. Device identifier code can be output by command inputs. 4. Refer to the table of command address and data input. Data is programmed, erased, or verified after mode setting by command inputs. 5. Status of automatic erase can be verified in this mode. Status outputs on I/O7. I/O0 to I/O6 are in high impedance state. 6. X : VIH or VIL. VPP = 0 V to VCC 5 HN28F101 Series Command Address and Data Input HN28F101 Series First cycle Second cycle ------------------------------ ------------------------------ The number Operation Address*2 Data*3 Operation Address*2 Data*3 Command of cycle mode*1 mode*1 ----------------------------------------------------------------------------------------------- Read (memory)*4 1 Write X 00H Read RA Dout ----------------------------------------------------------------------------------------------- Read identified codes 2 Write X 90H Read IA ID ----------------------------------------------------------------------------------------------- Setup erase/erase*5 2 Write X 20H Write X 20H ----------------------------------------------------------------------------------------------- Erase verify*5 2 Write EA A0H Read X EVD ----------------------------------------------------------------------------------------------- Setup auto erase/ 2 Write X 30H Write X 30H auto erase*6 ----------------------------------------------------------------------------------------------- Setup program/ 2 Write X 40H Write PA PD program*7 ----------------------------------------------------------------------------------------------- Program verify*7 2 Write X C0H Read X PVD ----------------------------------------------------------------------------------------------- Reset 2 Write X FFH Write X FFH ----------------------------------------------------------------------------------------------- Notes: 1. Refer to command program mode in mode selection about operation mode. 2. Refer to device identifier mode. IA = Identifier address, PA = Programming address, EA = Erase verify address, RA = Read address 3. Refer to device identifier mode. PA are latched by programming command. ID = Identifier output code, PD = Programming data, PVD = Programming verify output data, EVD = Erase verify output data 4. Command latch default value when applying 12 V to VPP is "00H". Device is in read mode after VPP is set 12 V (before other command is input). 5. All data in chip are erased. Erase data according to fast high-reliability erase flowchart. 6. All data in chip are erased. Data are erased automatically by internal logic circuit. External erase verify is not required. Erasure completion must be verified by status polling after automatic erase starts. 7. Program data according to fast high-reliability programming flowchart. 6 HN28F101 Series Absolute Maximum Ratings HN28F101 Series Parameter Symbol Value Unit ----------------------------------------------------------------------------------------------- All input and output voltage*1 Vin, Vout -0.6*2 to +7.0 V ----------------------------------------------------------------------------------------------- VPP voltage*1 VPP -0.6 to +14.0 V ----------------------------------------------------------------------------------------------- VCC voltage*1 VCC -0.6 to +7.0 V ----------------------------------------------------------------------------------------------- Operating temperature range Topr 0 to +70 C ----------------------------------------------------------------------------------------------- Storage temperature range*3 Tstg -55 to +125 C ----------------------------------------------------------------------------------------------- Storage temperature under bias Tbias -10 to +80 C ----------------------------------------------------------------------------------------------- Notes: 1. Relative to VSS. 2. Vin, Vout, VID min = -2.0 V for pulse width < 20 ns. 3. Device storage temperature range before programming. Capacitance (Ta = 25C, f = 1 MHz) Parameter Symbol Min Typ Max Unit Test condition ----------------------------------------------------------------------------------------------- Input capacitance Cin -- -- 6 pF Vin = 0 V ----------------------------------------------------------------------------------------------- Output capacitance Cout -- -- 12 pF Vout = 0 V ----------------------------------------------------------------------------------------------- 7 HN28F101 Series Read Operation DC Characteristics (VCC = 5 V 10%, VPP = VCC~VSS, Ta = 0 to +70C) HN28F101 Series Parameter Symbol Min Typ Max Unit Test condition ----------------------------------------------------------------------------------------------- Input leakage current ILI -- -- 2 A Vin = 0 to VCC ----------------------------------------------------------------------------------------------- Output leakage current ILO -- -- 2 A Vout = 0 to VCC ----------------------------------------------------------------------------------------------- VPP current IPP1 -- -- 20 A VPP = 5.5 V ----------------------------------------------------------------------------------------------- Standby VCC current ISB1 -- -- 1 mA CE = VIH ----------------------------------------------------------------------- ISB2 -- -- 20 A CE = VCC ----------------------------------------------------------------------------------------------- Operating VCC current ICC1 -- 6 15 mA Iout = 0 mA, f = 1 MHz ----------------------------------------------------------------------- ICC2 -- 10 30 mA Iout = 0 mA, f = 8 MHz ----------------------------------------------------------------------------------------------- Input voltage*3 VIL -0.3*1 -- 0.8 V ----------------------------------------------------------------------- VIH 2.2 -- VCC + 0.3*2 V ----------------------------------------------------------------------------------------------- Output voltage VOL -- -- 0.45 V IOL = 2.1 mA ----------------------------------------------------------------------- VOH 2.4 -- -- V IOH = -400 A ----------------------------------------------------------------------------------------------- Notes: 1. VIL min = -2.0 V for pulse width < 20 ns. 2. VIH max = VCC + 1.5 V for pulse width < 20 ns. If VIH is over the specified maximum value, read operation cannot be guaranteed. 3. Only defined for DC and long cycle function test. VIL max = 0.45 V, VIH min = 2.4 V for AC function test. 8 HN28F101 Series Test Conditions * Input pulse levels: 0.45 V/2.4 V * Input rise and fall times: 10 ns * Output load: 1TTL Gate + 100 pF (Including scope and jig.) HN28F101 Series AC Characteristics (VCC = 5 V 10%, VPP = VSS to VCC, Ta = 0 to +70C) * Reference levels for measuring timing: 0.8 V, 2.0 V HN28F101-12 HN28F101-15 HN28F101-20 ------------ ------------ ------------ Test Parameter Symbol Min Max Min Max Min Max Unit condition ----------------------------------------------------------------------------------------------- Address to output delay tACC -- 120 -- 150 -- 200 ns CE = OE = VIL ----------------------------------------------------------------------------------------------- CE to output delay tCE -- 120 -- 150 -- 200 ns OE = VIL ----------------------------------------------------------------------------------------------- OE to output delay tOE -- 60 -- 70 -- 80 ns CE = VIL ----------------------------------------------------------------------------------------------- OE high to output float*1 tDF 0 40 0 50 0 60 ns CE = VIL ----------------------------------------------------------------------------------------------- Address to output hold tOH 5 -- 5 -- 5 -- ns CE = OE = VIL ----------------------------------------------------------------------------------------------- Note: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. Read Timing Waveform Address CE Standby Mode t CE OE High WE t ACC Data Out t OE t DF t OH Data Out Valid Active Mode Standby Mode 9 HN28F101 Series Command Programming/Data Programming/Erase Operation DC Characteristics (VCC = 5 V 10%, VPP = 12.0 V 0.6 V, Ta = 0 to +70C) HN28F101 Series Parameter Symbol Min Typ Max Unit Test condition ----------------------------------------------------------------------------------------------- Input leakage current ILI -- -- 2 A Vin = 0 V to VCC ----------------------------------------------------------------------------------------------- Output leakage current ILO -- -- 2 A Vout = 0 V to VCC ----------------------------------------------------------------------------------------------- Standby VCC current ISB1 -- -- 1 mA CE = VIH ----------------------------------------------------------------------- ISB2 -- -- 200 A CE = VCC ----------------------------------------------------------------------------------------------- Operating Read ICC1 -- 6 15 mA Iout = 0 mA, f = 1 MHz VCC current ----------------------------------------------------------------------- ICC2 -- 10 30 mA Iout = 0 mA, f = 8 MHz ---------------------------------------------------------------------------------- Program ICC3 -- 2 10 mA ---------------------------------------------------------------------------------- Erase ICC4 -- 10 40 mA In automatic erase ----------------------------------------------------------------------- ICC5 -- 5 15 mA In high-reliability erase ----------------------------------------------------------------------------------------------- VPP current Read IPP1 -- -- 1 mA VPP = 12.6 V ---------------------------------------------------------------------------------- Program IPP2 -- 5 30 mA In programming ---------------------------------------------------------------------------------- Erase IPP3 -- 35 80 mA In automatic erase ----------------------------------------------------------------------- IPP4 -- 10 30 mA In high-reliability erase ----------------------------------------------------------------------------------------------- Input voltage VIL - 0.3*4 -- 0.8 V ----------------------------------------------------------------------- VIH 2.2 -- VCC + 0.3*5 V ----------------------------------------------------------------------------------------------- Output voltage VOL -- -- 0.45 V IOL = 2.1 mA ----------------------------------------------------------------------- VOH 2.4 -- -- V IOH = -400 A ----------------------------------------------------------------------------------------------- Notes: 1. VCC/VPP power on/off timing VCC must be applied before or simultaneously VPP, and removed after or simultaneously VPP. This VCC/VPP power on/off timing must be satisfied at VCC/VPP on/off caused by power failure. VCC 5V 0V 0s min 0s min 12V VPP 5V 0V 2. VPP must not exceed 14 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12 V. 4. VIL min = -1.0 V for pulse width < 20 ns. 5. If VIH is over the specified maximum value, programming operation cannot be guaranteed. 10 HN28F101 Series Test condition * Input pulse levels: 0.45 V/2.4 V * Input rise and fall times: 10 ns * Output load: 1TTL Gate + 100 pF (Including scope and jig.) HN28F101 Series AC Characteristics (VCC = 5 V 10%, VPP = 12.0 V 0.6 V, Ta = 0 to +70C) * Reference levels for measuring timing: 0.8 V, 2.0 V HN28F101-12 HN28F101-15 HN28F101-20 ------------ ------------ ------------ Test Parameter Symbol Min Max Min Max Min Max Unit condition ----------------------------------------------------------------------------------------------- Command programming cycle time tCWC 120 -- 150 -- 200 -- ns ----------------------------------------------------------------------------------------------- Address setup time tAS 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Address hold time tAH 60 -- 60 -- 60 -- ns ----------------------------------------------------------------------------------------------- Data setup time tDS 50 -- 50 -- 50 -- ns ----------------------------------------------------------------------------------------------- Data hold time tDH 10 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- CE setup time tCES 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- CE hold time tCEH 50 -- 50 -- 50 -- ns ----------------------------------------------------------------------------------------------- VPP setup time tVPS 100 -- 100 -- 100 -- ns ----------------------------------------------------------------------------------------------- VPP hold time tVPH 100 -- 100 -- 100 -- ns ----------------------------------------------------------------------------------------------- WE programming pulse width tWEP 70 -- 70 -- 80 -- ns ----------------------------------------------------------------------------------------------- WE programming pulse high time tWEH 40 -- 40 -- 40 -- ns ----------------------------------------------------------------------------------------------- OE setup time before command tOEWS 0 -- 0 -- 0 -- ns programming ----------------------------------------------------------------------------------------------- OE setup time before verify tOERS 6 -- 6 -- 6 -- s ----------------------------------------------------------------------------------------------- Verify access time tVA -- 120 -- 150 -- 200 ns ----------------------------------------------------------------------------------------------- Verify access time in erase tVAE -- 300 -- 300 -- 300 ns ----------------------------------------------------------------------------------------------- OE setup time before status polling tOEPS 120 -- 120 -- 120 -- ns ----------------------------------------------------------------------------------------------- Status polling access time tSPA -- 120 -- 150 -- 200 ns ----------------------------------------------------------------------------------------------- Standby time before programming tPPW 25 -- 25 -- 25 -- s ----------------------------------------------------------------------------------------------- Standby time in erase tET 9 11 9 11 9 11 ms ----------------------------------------------------------------------------------------------- Output disable time*3 tDF 0 40 0 50 0 60 ns ----------------------------------------------------------------------------------------------- Total erase time in automatic erase*3 tAET -- 30 -- 30 -- 30 s ----------------------------------------------------------------------------------------------- 11 HN28F101 Series HN28F101 Series Notes: 1. CE, OE, and WE must be fixed high during VPP transition from 5 V to 12 V or from 12 V to 5 V. 2. Refer to read operation when VPP = VCC about read operation while VPP = 12 V . 3. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 4. Address are taken into on the falling edge of write-enable pulse and addresses are latched on the rising edge of write-enabke pulse during chip-enable is low. Data is latched on the rising edge of write-enable pulse during chip-enable is low. Erase and Program Time Erase and program mode Min Typ*4 Max Unit ---------------------------------------------------------------------------------------------- Chip (128 kB) erase time Auto erase mode -- 1 30 second -------------------------------------------------------------------- Fast high-reliability erase mode*2, 3 -- 0.6 30 second ---------------------------------------------------------------------------------------------- Chip (128 kB) program time Fast high-reliability program mode*3 -- 5 81*5 second ---------------------------------------------------------------------------------------------- Notes: 1. Each values are same for all read access version. 2. Excludes pre-write process before erasure and verify process (6 s x 128 kB). 3. Excludes system overhead. 4. Ta = 25C, VPP = 12 V, VCC = 5 V 5. Theoretical value calculated from fast high-reliability programming flowchart. (25 s program + 6 s verify) x 20 times x 128 kB = 81 second. 12 HN28F101 Series Automatic Erase Timing Waveform Setup auto erase VCC VPP 12 V 5.0 V 5.0 V t VPS HN28F101 Series Auto erase & status polling t VPH Address CE t CEH OE t OEWS t CES t OEPS t CES t WEP t CWC t CES t CEH t WEP t AET t DF WE t DS I / O7 t DH Command in t WEH t DS t DH Command in t SPA Status polling I / O0 - I / O6 Command in Command in Status Polling Status polling allows the status of the flash memory to be determined. If the flash memory is set to the status polling mode during erase cycle, I/O7 pin is lowered to VOL level to indicate that the flash memory is performing erase operation. I/O7 pin is set to the VOH level when erase operation has finished. Notes: In automatic erase mode, the device automatically processes to pre-write all "0" before erasing. Therefore, it is not required to pre-write by fast high-reliability programming. 13 HN28F101 Series Fast High-Reliability Programming HN28F101 Series This device can be applied the fast high-reliability programming algorithm shown in following flowchart. This algorithm allows to obtain fasterprogramming time without any voltage stress to the device nor deterioration in reliability of programmed data. START Apply VPP= 12.0 0.6 V Address = 0 n=0 n + 1 n Write setup program command Write program address and data Wait 25 s Write program verify command Address + 1 Address Wait 6 s Verify GO NO LAST Address ? YES Apply VPP= V CC NOGO n = 20 YES NO END FAIL Fast High-Reliability Programming Flowchart Notes: In case of two or more devices are programmed simultaneously, following steps should be apllied to avoid over programming for the verified device . (1) Write set up program command to FFH, (2) Write program command to FFH, (3) Write program verify command to 00H and program verify address to read address. 14 HN28F101 Series Fast High-Reliability Programming Timing Waveform Setup program VCC VPP 5.0 V 12 V 5.0 V t VPS Program HN28F101 Series Program verify tVPH Address valid tAH Address t AS CE t CEH OE t OEWS WE tDS I / O7 Command in t CES tCWC t PPW tCES t WEP t CES t WEP tWEP t CEH t CEH t OERS t DF Data out valid t WEH tDH tDS Data in tDH tDS tDH Command in t VA I / O0 to I / O6 Command in Data in Command in Data out valid Notes: The data output level during program verification may result in an intermediate level between VOH and VOL due to an insufficiently programmed. 15 HN28F101 Series Fast High-Reliability Erase HN28F101 Series This device can be applied the fast high-reliability erase algorithm showm in following flowchart This algorithm allows to abtain faster erase time without any voltage any voltage stress to the device nor deterioration in reliability of data. START YES All bits DATA = 00H? NO All bits program 00H *1 Set address n=0 n+1 n Write setup erase / erase command Wait 10 ms Write erase verify command Address + 1 Address Wait 6 s Verify YES NO NO NO LAST Address ? YES END FAIL n = 3000 YES *1. Program data to all bits according to fast high-reliability erasing flowchart. Fast High-Reliability Erasing Flowchart Notes: In case of two or more devices are erased simultaneously, following steps should be applied to avoid over erase for verified device. (1) Write set up erase command to A0H and set erase verify address to verify address. (2) Write erase command to A0H. (3) Write erase verify command to A0H. 16 HN28F101 Series Erase Timing Waveforms HN28F101 Series Setup erase VCC VPP 5.0 V Address 5.0 V 12 V t VPS Erase Erase verify t VPH Address valid t AS tAH CE OE tOEWS t WEP t CES t CWC t CES tCEH t CEH t WEP t CES t ET t WEP t CEH t OERS t VAE WE t DS t DH I/O0 to I/O7 Command in Command in Command in t WEH t DS t DH t DS t DH Data out valid t DF Notes: The data output level during erasure verification may result in an intermediate level between VOH and VOL due to an insufficiently erased. 17 HN28F101 Series Mode Description Device Identifier Mode HN28F101 Series The device identifier mode allows the reading out of binary codes that identify manufacturer and type of device, from outputs of flash memory. By this mode, the device will be automatically matched its own corresponding erase and programming algorithm, using programming equipment. HN28F101 Series Identifier Code A0 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Hex (12) (21) (20) (19) (18) (17) (15) (14) (13) Identifier TSOP (20) (29) (28) (27) (26) (25) (23) (22) (21) Data ----------------------------------------------------------------------------------------------- Manufacturer code VIL 0 0 0 0 0 1 1 1 07 ----------------------------------------------------------------------------------------------- Device code VIH 0 0 0 1 1 0 0 1 19 ----------------------------------------------------------------------------------------------- Notes : 1. Device identifier code can be read out by applying 12.0 V 0.5 V to A9 when VPP = VCC, or inputting command while VPP is 12 V. 2. A1 to A8, A10 to A16, and CE = OE = VIL, WE = VIH 3. VCC = VPP = 5 V 10% DIP. SOP, PLCC Pins 18 |
Price & Availability of HN28F101FP-15
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |